1. Field of the Invention
The present invention relates to a design system of an integrated circuit and a design method and program of the integrated circuit and, more particularly, to the design system of the integrated circuit in order to analyze and adjust timing in the integrated circuit when designing the layout of the integrated circuit.
2. Description of the Related Art
In recent years, the layout design, which organizes the arrangement of respective circuit elements (e.g. logic gates) composing the integrated circuit on a chip and wiring between these circuit elements, has been complicated as the integrated circuit becomes large in scale and high-speed and the process becomes refined. The conventional layout design carries out physical layout on an actual chip, or the arrangement of respective circuit elements and wiring between these circuit elements based on circuit-connection information of the logic image which is made by hardware description language or the like. Such a layout design is generally made by using software.
Whether the timing error that disturbs the normal operation of a circuit exists in one circuit of which layout is arranged, is tested by a timing analysis, based on such information as a net list which shows circuit elements composing the arranged circuits and their wirings.
Details of the timing error will be explained with reference to FIGS. 5 and 6.
FIG. 5 is a schematic circuit diagram for explaining what the timing error is. FIG. 6 is a timing chart showing one example of operation in the circuit shown in FIG. 5.
In FIG. 5, the reference numbers 41,43 designate D-type flip-flops (hereinafter referred to “DFF”). The number 42 is a combination circuit for a logical operation such as addition and multiplication rules of arithmetic.
A signal DT1 input to a DFF41 is outputted as a signal DT2 from the DFF41 synchronizing a rise time (e.g. at a time T12 in FIG. 6) of a clock signal CLK. The signal DT2 is input into and specifically and logically operated in the combination circuit 42. The operation result in the combination circuit 42 is outputted as a signal DT3 and input to the DFF 43.
The time at that the signal DT3 outputted from the combination circuit 42 is sent to the DFF 43 lags behind the time at that the signal DT2 is outputted from the DFF 41 (time lag). This time lag is caused by the arithmetic operation in the combination circuit 42 and by the wiring as a propagation path over which signals are sent between the DFFs 41 and 43 via the combination circuit 42.
A sequence circuit such as the DFF, which captures an input signal with synchronizing a synchronizing signal (e.g. clock signal), defines therein a set-up time Ts for determining and holding the input signal before capturing the input signal. The sequence circuit also defines therein a hold time Th during which the input signal does not change and remains after capturing the input signal at its capturing time. A state in which these defined times Ts and Th are not assured is called a timing error. Other states except for the defined set-up time Ts are called set-up errors. Other states except for the defined hold time Th are called hold errors.
The timing error will be explained in detail with reference to FIG. 6. Signals CLK, DT1, and DT2 in FIG. 6 are the same with those in FIG. 5. Signals DT3-A to DT3-C are one particular details of the signal DT3 shown in FIG. 5. The signal DT3-A does not indicate the timing error of the signal DT3, while the signal DT3-B brings about the timing error (Set-up error) of the signal DT3 and the signal DT3-C also brings about the timing error (Hold error) of the signal DT3.
Taking an instance shown as the signal DT3-A in FIG. 6, the time lag because of the signal propagation between the DFF 41 and the DFF 43 is later than the hold time of the DFF 43 and earlier than a time (T-Ts) which subtracts the set-up time Ts of the DFF 43 from the clock cycle T. The signal DT3-A changes after the hold time Th and before the set-up time Ts for the next rise time T13 of the clock signal CLK. As a result, no timing error appears in the circuit shown in FIG. 5, which ensures the normal operation.
Taking another instance as the signal DT3-B in FIG. 6, when the time lag because of the signal propagation between the DFF 41 and the DFF 43 is later than a time (T-Ts) which subtracts the set-up time Ts of the DFF 43 from the clock cycle T, the change time of the signal DT3-B does not satisfy the definition of the set-up time Ts for the time T13. The thus-outputted signal (data) from the DFF 41 is propagated too late to the downstream DFF 43. As a result, the timing error (Set-up error) appears in the circuit shown in FIG. 5.
Taking still another instance as the signal DT3-C in FIG. 6, when the time lag because of the signal propagation between the DFF 41 and the DFF 43 is earlier than the hold time Th of the DFF 43, the signal DT3-C changes during the hold time Th for the time T12, which does not satisfy the definition of the hold time Th. The thus-outputted signal (data) from the DFF 41 is propagated too early to the downstream DFF 43. As a result, the timing error (Hold error) appears in the circuit shown in FIG. 5.
In a design of the integrated circuit, when such timing errors appear in the circuit of which layout is arranged from the timing analysis results thereof, the timing is adjusted to recover the timing error. The actual timing adjustment is to change the arrangement of circuit elements and their wiring, or to change the circuitry (by adding a buffer).
The timing adjustment is required whenever the set-up error or the hold error is recognized in the timing analysis test. The timing adjustment to recover the set-up error is generally carried out first since it may difficult to be independently recovered with no harm to others, and thereafter the hold error is recovered.
The conventional design method of the integrated circuit requires to carry out the layout re-designing and timing analysis re-testing whenever the timing is adjusted to recover the set-up error and hold error respectively that are recognized above in the timing analysis test.
Meaning that when designing the layout, which finally determines the arrangement of respective circuit elements composing the integrated circuit on a chip and wiring between these circuit elements, the conventional design method of the integrated circuit requires to carry out such layout design operations as; a first layout design→the first timing analysis/test→the first timing adjustment (Set-up error adjustment)→a second layout design→the second timing analysis/test→the second timing adjustment (Hold error adjustment)→a third layout design→the third timing analysis/test.
The layout design is also time-consuming despite the use of software or the like since the integrated circuit recently becomes large in scale (due to an increase in the number of gate composing one integrate circuit).
The operations starting from the first timing adjustment (Set-up error adjustment) are again required when a new set-up error that appears in the second timing adjustment (Hold error adjustment) is recognized in the third timing analysis/test. Thereby the conventional layout design process requires to carry out the layout design, timing analysis test, and timing adjustment repetitively until no timing errors appear in the circuit of which layout is arranged.
Therefore, it is time-consuming to design the layout where all timing errors are recovered (restored) to organize the arrangement of respective circuit elements on a chip and wiring between these circuit elements.